In IC technology there is a need to stack chips together to form multi-tiered (3-D) IC devices (also referred to as multi-layered IC devices or stacked IC devices). This is ordinarily accomplished in one of two ways: wafer-to-wafer bonding or die-to-wafer bonding.
Wafer-to-wafer bonding generally describes a technique where the wafers are aligned and bonded face to face or back to face and then thinned and interconnected prior to additional stacking processes or dicing. Wafer-to-wafer bonding has the advantage of a high throughput, but generally results in low yield percentages. The low yield arises from the random location of defective sub-devices within the wafers to be stacked. The cumulative yield of the stacking process is approximately the product of the individual tiers yields in the stack furthermore the wafer-to-wafer bonding has a requirement that the die size be the same between the tiers to be bonded.
Die-to-wafer bonding generally describes a technique where individual die from a “donor” wafer are cut from the donor wafer and subsequently aligned with die (that have not been cut) from a “receiver” wafer. Although die-to-wafer bonding has a higher yield than wafer-to-wafer bonding and does not require the die to be the same size, it results in a lower throughput because each die needs to be aligned with its corresponding die on the receiver wafer. The challenge that accordingly arises is the reduction of time and cost associated with aligning each die to a receiver wafer.